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Comparator to Detect Three or More Bits in Error in a Memory Word

IP.com Disclosure Number: IPCOM000039700D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Geneste, M Poiraud, C [+details]

Abstract

The data words stored into a memory may be in error due to a hardware failure of the memory cells. The failures in memory cells cause the bits which are read from these cells in error to be stuck at one or zero. Two bits in error are corrected by the memory error correction circuit, and the detection of three bits or more in error is to be reported to the device incorporating the memory. The logic shown in the Fig. 1 allows this operation to be performed. The word W which is read from a memory location is inverted. The inverted word is written into the same memory location and read. The word W' which is read is compared with W. The comparison allows a hardware failure to be detected. The words W and W' are provided to an XOR arrangement.