Browse Prior Art Database

HYBRID DIFFERENTIAL CASCODE CURRENT SWITCH SHIFT REGISTER LATCH

IP.com Disclosure Number: IPCOM000039716D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Bello, SE Bergenn, RO Chu, WM Eichelberger, EB [+details]

Abstract

The invention is a modified (hybrid) differential cascode current switch (DCCS) shift register latch (SRL) suitable for placement in a gate array environment in which emitter-coupled logic (ECL) elements from the basic logic cells for VLSI construction. The invention permits the DCCS SRL to interface directly with the ECL circuitry. ECL VLSI circuits are typically standardized in supply voltage to as small a value as possible to minimize power dissipation on the chip, while maintaining reliable operation. A problem encountered when "retrofitting" a DCCS SRL to that standardized environment is that the input signal voltages from the ECL logic elements are single ended, rather than differential, and thus can cause saturation of the transistors in the DCCS SRL array, impairing its operation.