Browse Prior Art Database

Passivated Recess-Gate Structure

IP.com Disclosure Number: IPCOM000039724D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Buchmann, P Van Zeghbroeck, B [+details]

Abstract

In the proposed recess-gate structure, the semiconductor substrate, with an n-type channel and an n+ contact layer on top of it, is covered with a nitride layer serving as passivation and, after patterning, as mask for an isotropic recess etching process which results in well-controlled self-alignment distances between the gate and the recess also for sub-micron gate lengths. The proposed recess-gate structure is shown in the figure. The fabrication starts with a buried p-layer, an n-type channel layer, an n+ contact layer, grown, for example, by molecular beam epitaxy. The whole structure is then covered with a layer of Si3N4 .