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A Shorted-Path Diagnostic for the Physical Design of an Integrated Circuit Chip

IP.com Disclosure Number: IPCOM000039775D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Clark, K Koehler, GG [+details]

Abstract

During verification of the layout or physical design of a circuit, the determination of which wires undesirably short two or more schematic nets together can be performed with this method. Each contact in the single physical net is assigned to one of the schematic nets based upon its identifier. The shorted path is determined when a series of wires or shapes is found which links a contact or wire from one of the schematic nets to a contact or wire from a different schematic net. A short is defined as an error in the physical representation of a circuit such that two or more schematic nets are incorrectly represented in the physical implementation by just one physical net. Three steps are performed in the identification process for shorted nets. These steps are contact classification, path identification and path minimization.