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Technique for Alignment and Power Leveling in Optical VLSI Testing

IP.com Disclosure Number: IPCOM000039778D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Scheuermann, M [+details]

Abstract

This publication describes a scheme for aligning an array of photodetectors with an array of optical waveguides. This described technique can also be used to detect the relative optical power absorbed in each photodetector. It is known that an optical space transformer for high speed VLSI testing is advantageous. This technique is practical only if it is possible to align an array of optical waveguides which carry optical signals to the chip with a corresponding array of photodetectors on the chip. The alignment requirements may be quite stringent for photodetector spacing of 20-40 microns. To accomplish the alignment, the photodetector themselves can be used as positional detectors. The waveguide array can be mounted on a high precision XYZ positional stage.