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Exception (Error) Controls for an Asynchronous Memory Interface in a Two-Processor Computer System

IP.com Disclosure Number: IPCOM000039790D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Moore, CR Sotolongo, H [+details]

Abstract

A technique is described whereby a logic circuit provides a means of controlling exceptions (errors) in a two-processor computer system which operate independently using their local memory units, but which have the ability to share data in one of the processors. Two special control states are implemented, when an exception condition is detected, so as to synchronize the execution of storage operations. The data flow control structure of a two-processor system as it connects to the storage control unit (SCU) is shown in the figure. Exception conditions may occur in many forms, such as the logic signaling an error, software-related conditions to protect any violation of the instructions, or address translations errors, to name a few.