Browse Prior Art Database

Direct Memory Access Enhancement

IP.com Disclosure Number: IPCOM000039792D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Krull, JW Le, AV Oliva, FG Roesel, GL Ruth, DB Sotolongo, H [+details]

Abstract

A technique is described whereby the performance of direct memory access (DMA), as used in a storage control unit (SCU), is enhanced through the use of a DMA_Reserve line, in computer systems. The DMA_Reserve line expedites the handling of DMA operations by eliminating needless instruction fetch storage cycles. The computer system, as shown in Fig. 1, contains an SCU, a system bus adapter (SBA) and a processor bus (Pbus) for connection to the processors (PU). The SCU provides the interface to main storage for both the PU and the SBA. The SBA provides the interface between input/output (I/O) bus peripherals and main storage via the SCU. The processor bus (Pbus), and related control signals provide the means for communication between any two of the SCU, the PU and the SBA.