Critical Path Design on Data Flow Chip
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Data path design on data flow chips typically involves approximately three stages of delays from input to output in a given chip. This is true when more than one path could drive a data bus. However, if one path is determined to be more critical than the other paths, this would allow two stages to be removed and result in the critical path becoming much faster. Such a data path design is described in the following. Fig. 1 shows a typical data path design with competing paths into the driver. By allowing the critical path direct access to the driver, and to any other path through a multiplexer, the path to a single stage delay is reduced. Fig. 2 shows the reconfigured design with the critical path having direct access to the driver.