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Process for Making Very Small, Asymmetric, Field-Effect Transistors

IP.com Disclosure Number: IPCOM000039819D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Nowak, EJ [+details]

Abstract

A process is described for making field-effect transistors (FETs) having a lightly doped drain (LDD) and an abrupt junction at the source. Dimensions are smaller than current photo resolution allows by the use of sidewall techniques. Thus, very small, asymmetric LDD FETs are constructed having only 1/2 the resistance penalty of symmetric LDDs. Fig. 1 shows the results of first forming a series of film layers: a gate insulator 4, gate conductor (e.g., polysilicon) 6, and a mandrel-forming material 8 on silicon wafer 2. Next, an edge is formed in material 8 by photoetching. A conformal layer 10 is deposited over the surface and reactive ion etching (RIE) is used to remove the conformal layer from all planar surfaces, leaving only a sidewall coating of film 10, as shown.