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Soft Error Rate Reduction by Isolation Trench Extension

IP.com Disclosure Number: IPCOM000039830D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Hsieh, CM O'Brien, RR [+details]

Abstract

A method has been proposed to mitigate the soft errors produced in semiconductor devices by alpha particles. The proposal suggests intercepting the shallow angle tracks below the subcollector by deep trench isolations. In the device, a low angle track of excess carriers (Fig. 1) can distort the junction field of the subcollector 2 and the substrate 3 and funnel carriers into the subcollector which is located near the bottom of the isolated trench 4. Previously, buried high doped layers of various types and shapes were used to provide a barrier to excess carrier collection. Complicated processing was required to provide such barriers which could have an effect on device characteristics. It is suggested to make the isolation trenches (Fig.