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Interface Protocol for Attachment of BUS Units Having Limited I/O Pins to Processors Utilizing Several Buses Disclosure Number: IPCOM000039835D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue


Related People

Float, GD Furney, RW Malmquist, CA Wilson, JD [+details]


A requirement that every bus unit in a system be attached to all processor busses may cause the system layout to be repartitioned due to the limited number of inputs/outputs available on a card or on logic chips. This could result in the need for additional cards or chips to be installed and, in the process, limit the number of feature cards that could be used. This interface scheme allows a bus unit with limited I/O pins, either on the card or the logic chips, to be logically attached to a processor having several busses which transfer data on a single system cycle in the following manner. (Image Omitted) The scheme allows one or more Bus Units with limited I/O pins, i.e., a Slave Bus Unit (SBU), to be attached to a processor via a Bus Unit, which does have total bus interface with the processor, i.e.