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Time Delay Circuit for Pulse Signal

IP.com Disclosure Number: IPCOM000039845D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Coburn, RL Hong, JH Stakely, BL [+details]

Abstract

This article describes a time delay circuit for digital signals which is suitable for integrated circuit implementation with one off-chip capacitor. Lumped LC delay line or a clocked digital delay are commonly used to provide time delay to digital circuits. Lumped LC delays have several drawbacks: a new line must be specifically designed for each new application, they are relatively large (1" to 7") and expensive due to the high quality components needed to minimize signal distortion, they tend to distort the input waveform and, most importantly, these (Image Omitted) types of delay lines are impossible to integrate on a silicon chip. The digital circuits also have drawbacks, such as the need for an external clock, not being able to provide fine granularity of delay, and excessive chip real estate and power dissipation.