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Noise Reduction Method for VLSI Logic Chips

IP.com Disclosure Number: IPCOM000039884D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Haug, W Loehlein, W Tong, MH [+details]

Abstract

Very large-scale integrated (VLSI) logic chips are often designed to meet performance requirements at worst case (WC) process biases and WC low power supply voltage. However, at best case (BC) process biases and BC high power supply voltage, the chips then operate at very high speed, generating a high noise. The noise, if high enough, will cause chip failures, such as latch-up and inadvertent latch set. This article describes a noise reduction method. Depending upon the process biases, the power supply voltage is chosen to match the VLSI logic chip set. The faster the chips, the lower the chosen voltage will be. As a result, the noise can be contained at all process biases. A diagram of the disclosed noise reduction scheme for a complete system, such as a personal computer, etc., is shown in Fig. 1.