On-Chip Decoupling Capacitor for Logic VLSI Chips
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
Power supply noise reduction is achieved by distributed on-chip decoupling capacitors provided and integrated in logic VLSI chips, the logic cells of which are realized in CMOS technology. Unused cells are modified to form the capacitors connected to power supply line VH and to ground GD. Power supply noise is mainly due to current changes WI/Wt in the inductances of the module and chip wiring. These current changes are caused by the switching of the logic circuits and the embedded arrays. As normally only 60% of the cells of logic chips are used, unused cells are employed as distributed decoupling capacitors between power supply line VH and ground GD, thus reducing the power supply noise. A trade- off between noise and the number of switching circuits is possible.