SLS - a FAST SWITCH LEVEL SIMULATOR for VERIFICATION and FAULT COVERAGE ANALYSIS
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01
The switch level simulator (SLS), consisting of a compiler and a monitor, when implemented with a series of algorithms and operated in conjunction with high speed computers, is capable of analyzing the electrical behavior of MOS transistor circuitry. SLS provides high speed switch level simulation, so as to provide MOS (metal-oxide semiconductor) circuit network design verification/checking of applications and for estimating fault coverage. The essential element of the SLS is to provide as close a representation of the physical structure of the circuits as possible. Also, the SLS must provide high speed analysis and determination of the faults. The SLS described herein has the ability of achieving analysis performance of up to 10 simulation cycles per second for 100,000 device networks.