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Carry Signal Generation for High-Speed Full Adder

IP.com Disclosure Number: IPCOM000039903D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Helwig, K [+details]

Abstract

An improved circuit for generating the carry signal is described in conjunction with XOR circuit and (CMOS) inverters forming full adder circuits (Figs. 1 and 2) with inputs A, B, Cin and outputs S and Cout for the sum and carry-out function, respectively. The carry circuit consists of two P-FETs T1 and T4 and two N-FETs T2 and T3 which are used as transfer devices. The sources of these four FETs are driven by CMOS inverters I, whereas the gates are controlled by the true and inverted output X, X- of the XOR1 circuit. The structure of the carry circuit may be kept substantially identical for the carry-out true (Fig. 2) and the carry-out complement (Fig. 1) function, the only exception being the crossing of the X and the X- signal lines, as indicated in Fig. 2.