Browse Prior Art Database

Folded Bitline Configuration

IP.com Disclosure Number: IPCOM000039905D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Hwang, W Lu, NCC [+details]

Abstract

Dynamic random-access memory cells can be constructed with greater density by using folded bitlines each connected to alternate cells or by slightly offsetting adjacent cells in rows and columns. Fig. 1 schematically illustrates a memory cell having trench capacitors 1 and 2 in substrate 3 each connected to a respective source 4 and sharing a common drain junction 5 and common bitline 6. Word lines 7 and 8 are connected to respective polysilicon transfer gates. The bitline is constructed using one layer of interconnection line among its associated cells. An arrangement for folded bitlines is shown in Fig. 2. True bitlines BL1-BL4 and complementary bitlines BL1-BL4 interconnect in zigzag fashion with bitline contacts 10 in alternate columns.