Browse Prior Art Database

FABRICATION of BURIED MEMBRANE for SUPERCONDUCTING TRANSISTOR DEVICE

IP.com Disclosure Number: IPCOM000039907D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Brady, MJ Gallagher, WJ Speidell, JL [+details]

Abstract

An improved superconducting transistor and a method for fabricating the same are disclosed. The transistor basically comprises drain and source metallurgy atop a patterned SiO2 layer, followed by a crystal silicon layer which has had oxygen or nitrogen implanted into it to cause the formation of three layers (silicon, a buried insulator, and silicon) including an extremely thin buried insulator layer, wherein the third silicon layer has been pattern etched to the buried insulator, followed by a thermal oxide layer and gate metallurgy layer. The improved superconducting transistor is similar to one proposed in the art, but uses the implanted buried insulator to replace the heavily boron-doped thin silicon membrane proposed in the art.