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Reading L2* and Gated B Clock Shift Register Latches Using a Bring-Up Tool to Scan Out the Values While Preserving Machine State

IP.com Disclosure Number: IPCOM000039914D
Original Publication Date: 1987-Aug-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Sotolongo, H [+details]

Abstract

This article describes a technique for reading L2* and gated B clock shift register latches using a bring-up tool to scan the values without destroying the machine state. Fig. 1 is a representation of a shift register latch (SRL). It consists of two transparent latches interconnected as shown. The L1 latch has two sets of data and clock ports. The D and C inputs are the data and clock inputs for normal functional operation of the latch. The I and A inputs are the data and clock inputs used in scan mode. The B input is the clock input for the L2 latch. The outputs labeled L1+, L2+, etc., are the positive and negative polarity outputs for the respective latches. Transparent latch means that when the clock is active (in this case high level by definition) the output will follow the data input for that latch.