Tolerance-Compensated Circuit for Cmos Vlsi Clock Distribution
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
In a conventional computer system, clock distribution on chip clocks is distributed through a tree of AND-OR logic and clock drivers, as seen in Fig. 1. Chip-to-chip clock tolerance is defined as the difference between worst-case delay and best-case delay of the clock tree measured from point A to point B. This tolerance is due to process variation, temperature difference, and supply voltage variation. Because of the clock tolerance, longer machine cycle is incurred which reduces machine performance. If the delay differences between worst-case delay and best-case delay of each logic stage used in the clock distribution tree are reduced, the tolerance of the whole tree can therefore be reduced. The tolerance of each stage can be reduced by using PMOS pull-up loads which are biased with a special tolerance detector circuit.