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TECHNIQUES for PARASITIC CAPACITANCE MINIMIZATION

IP.com Disclosure Number: IPCOM000039979D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Hoffman, CR [+details]

Abstract

In the design of integrated circuits, ideal circuit elements (i.e., transistors, resistors and capacitors) cannot be obtained because of the unavoidable presence of parasitic elements. These parasitic elements, which are a function of the physical dimensions and layout of the devices, as well as the doping profile, result in a deterioration of performance. In MOSFET circuits where nodal impedance is inherently (Image Omitted) high, even small amounts of parasitic capacitance can affect the high frequency response of amplifying circuits. The following discussion provides techniques for minimizing the parasitic capacitance associated with resistor and transistor elements in a MOSFET process. When P-N junction isolation is used as seen in Fig.