Browse Prior Art Database

High Speed Message Buffers for Input/Output Processors to Minimize Buffer Not-Available Messages

IP.com Disclosure Number: IPCOM000039995D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Chisholm, DR [+details]

Abstract

A technique is described whereby high speed data buffers, and associated logic circuitry, enable various input/output computer processors to maximize the utilization of a single shared input/output (I/O) bus. So as to maximize the utilization of the I/O bus, data is buffered into three slave message buffers so as to minimize the number of buffer not-available (BNA) occurrences. Typically, an I/O bus is an asynchronous bus which supports a multiple number of I/O bus units (IOBU) and is a term for any bus unit which is addressable on the I/O bus, which may be input/output processors (IOPs), the central processing unit (CPU) or a processor sharing IOPs. IOP 11, as shown in Fig. 1, is typical of an input/output processor, utilizing Base-Z 10 to control the transfer of data between host processor 12 and I/O devices 21, 22 and 23.