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High Speed Data Buffer to Allow Multiple Computer Processors to Operate With Different Transfer Rates Disclosure Number: IPCOM000039997D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

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Chisholm, DR [+details]


A technique is described whereby a high speed data buffer, and associated logic circuitry, enables various input/output computer processors, which incorporate different transfer rates, to maximize the utilization of a single shared input/output (I/O) bus. So as to maximize the utilization of the I/O bus, data is buffered and transferred entirely in packet format, rather than implementing transfers on an "as available" basis. Typically, an I/O bus is an asynchronous bus which supports the processing attachments of various input/output bus units (IOBUs) which operate at different speeds. An IOBU may be any bus unit that is addressable on the I/O bus, such as an input/output processor (IOP), central processing unit (CPU) or a processor sharing an IOP.