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Sticky Bit Generation for IEEE Floating-Point Multiplication

IP.com Disclosure Number: IPCOM000039999D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Keung, TW [+details]

Abstract

This article describes a scheme to generate the sticky bit for floating-point (FP) multiplication. The sticky bit is generated for the IEEE standard of FP multiply operation, based on Booth's algorithm. It utilizes the existing carry lookahead (CLA) final adder, together with a minimum amount of logic, for the sticky-bit generation. Thus, a logic saving is achieved, as well as avoiding additional FP multiply execution cycles. The approach is adaptive to other multiply units without a final adder, through the addition of a spill adder. (Image Omitted) The multiply chip set is a uni-format dual-function multiply FP processor. All the input operands to the multiply chips are treated as uni-format FP numbers with a fraction of 64 bits (double extended format).