Browse Prior Art Database

Dual-Pin Wafer-Alignment System

IP.com Disclosure Number: IPCOM000040037D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Kaufman, CL Meranda, KW Sargent, DR [+details]

Abstract

This article describes a system to reduce the theta error alignment time which utilizes the wafer notch for consistent chip orientation. This new system reduces wafer alignment time from twenty to five seconds/wafer, and thus significantly increases throughput. The dual-pin alignment system was developed to take advantage of notch consistency. Fig. 1 shows pins 10 and 12 placed on chuck 14 with their distance from the chuck center depending on the size of wafer 16. Wafer 16 is placed on chuck 14 and oriented to locate notch 18 around pin 10. Wafer 16 is then rotated around pin 10, in the direction indicated by arrow 20 in Fig. 2, until edge 22 contacts pin 12. Now, chuck vacuum is turned on to secure the wafer at this location. Alignment is checked and fine tuned with the existing alignment system.