Browse Prior Art Database

Peripheral Logic for Writable Control Stores

IP.com Disclosure Number: IPCOM000040042D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Mori, F [+details]

Abstract

This article describes peripheral logic for writable control stores (WCSs) associated with a bit slice sequencer. The logic has a configuration employing universal shift registers (USRs) for transfer of data to and from the WCSs. This configuration enables the reduction of necessary parts, substrate space and cost in contrast to conventional arrangements using transceivers and pipeline registers. The figure shows an embodiment including plural WCSs, i.e., WCS1 plural USRs, i.e., USR1 ... USRn+2, and a bit slice sequencer. Each USR has both serial and parallel data transfer functions. The USR2 - USRn+2 are connected in series to shift data bits serially through them. In initial loading or diagnosing, the data (i.e.