Browse Prior Art Database

Novel Process for Eliminating Salicide Bridging

IP.com Disclosure Number: IPCOM000040048D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Barber, JR Kotecha, HN Stanasolovich, D [+details]

Abstract

This article describes a process for eliminating shorting between a source or drain and the gate of an FET in a salicide process. Referring to Fig. 1, a substrate 10 has source and drain regions 12, 14 defined. Silicon oxide layer 16 overlies the substrate 10 and source and drain regions 12, 14. Polysilicon gate 18, interfacial oxide 19, and silicon nitride layer 20 are subsequently deposited and lithographically defined and etched. Following the gate definition steps, a thin conformal coating of silicon oxide is then deposited and unisotropically etched, leaving oxide spacers 22 (Fig. 2). The source and drain regions 12 and 14 are then ion implanted, as customary.