Browse Prior Art Database

Optimization Techniques for Recirculation Hardware Sorter

IP.com Disclosure Number: IPCOM000040051D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Ashley, DJ Hassebrook, L [+details]

Abstract

A previously described sorting method [*] accomplished sorting by recirculating an entire vector of operands through a hardware sorter (linear systolic array) until an "order count circuit" recognized sorted order throughout the vector of operands. The operands are retrieved from storage by use of read/write address registers which are initially set to the address of the first operand in the vector. The operands were accessed from memory sequentially until the last vector (Image Omitted) operand address resided in the read/write registers. The registers' address was then reset to the first operand for subsequent passes, such that the entire vector of operands was cycled through the sorter for each pass until order was recognized. Storage access time is the largest delay time associated with hardware sorting.