Method for Displaying Embedded Arrays Using ECIPT Latches
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
Electronic chip-in-place testing (ECIPT) drivers were implemented in order to enhance testing capabilities. ECIPT permits the scanning of a chip to obtain its values being driven off chip without physically probing the chip. To accomplish this, a latch is associated with each driver and is wired into a normal level sensitive scan design (LSSD) scan ring . The latch is clocked with an external signal which also causes the driver to go to a tri-state level. This signal is called "scan mode". During scanning, scan mode is in such a state as to freeze the contents of the latch. When not scanning, scan mode looks like a "hot clock", allowing the data at the input of the latch to flush directly through to the driver.