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Branchable INSTRUCTION BUFFER for Cacheless Machines

IP.com Disclosure Number: IPCOM000040071D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Curley, LD Kuruts, JP [+details]

Abstract

The purpose of a cache is to allow the fast accessing of instructions and to free main storage from re-accessing instructions each time they are repeated. In a system without a cache a means of preventing the instruction fetch process from tying up the main storage interface with repeated instruction fetches is needed. One method of accomplishing this is to implement a fully accessible dual-port instruction buffer with such features as immediate access to any loaded instruction, parallel read and write capability, partial buffer load capability with a marking system to keep track of valid entries, and wait capability for a branch ahead in the buffer to entries not yet loaded from memory. There are a few natural additions to this buffer which make it more flexible for non-sequential execution. 1.