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Low Inductance Chip Carrier With Decoupling Capacitors

IP.com Disclosure Number: IPCOM000040103D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Churchwell, RW Oberschmidt, JM [+details]

Abstract

This design reduces the induced voltage for chips in semiconductor packages. A multi-layer ceramic (MLC) interposer is put between the chip and the substrate. Then appropriate capacitors are attached to the sides of the interposer. In semiconductor packages, it is sometimes desirable to place capacitors close to the chip to provide low inductance, to reduce delta-I noise, and to prevent false signals. Fig. 1 shows use of a chip carrier or interposer 5 to which the chip 2 and a capacitor 1 may be joined by C-4 solder contacts 3 and solder bar contacts 11, respectively. Vias 9 connect to the MLC substrate 6 through C-4 contacts. In Fig. 2, metal layers 7 are interspersed with ceramic layers 8 throughout the interposer 5. Metal tabs 10 connect to the power vias, with each layer having a different voltage from its neighbor.