Simplified Cascode Reference Generation
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01
A typical cascode current switch circuit (Fig. 1), which can be used in very large-scale integration logic chips, has a 3.4v power supply to define two cascode signal levels. (A two-way XOR function is depicted.) One level is centered around Vref-1, and the other is centered around Vref-2. These two voltage references are distributed throughout the chip, and they are generated by on-chip reference circuits. For a good output drive capability, the outputs are generated (Image Omitted) by emitter follower stages. Both the current switch and the emitter followers are biased with constant current sources, which are driven by another distributed reference voltage (Iref).