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Low End Ibm System/370 Data Processing System Direct Memory Access Disclosure Number: IPCOM000040119D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

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Bogusky, MJ Callahan, RW Oliver, BL Preston, DC [+details]


A data processing system design (Fig. 1) allows the high speed exchange of data between different memories and input/output (I/O) devices in which the I/O device is controlled by one processor but is reading data from the memory of another processor. The design consists of a processor 1 serving as an I/O controller, a 68000 processor-based card 2 (not seen) serves the function of a 370 processor and a multipurpose interposer adapter 2 attached to a hard disc 3 provides the function of a high speed hard disk for mass storage. The attachment of the adapter 2 is through a universal controller I/O bus adapter (not seen) attached to a universal controller I/O bus 4. This scheme did not take full advantage of the transfer capabilities of the multipurpose interposer adapter 2.