Browse Prior Art Database

Memory Bus Switch Logic Unit

IP.com Disclosure Number: IPCOM000040135D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Moriguchi, S Yokoo, S [+details]

Abstract

In a terminal controller comprising multiple control units and memory banks in which one of the control units is for controlling the communication with a main controller or host processor connected thereto and for receiving instructions and data for the other control units from the main controller and selectively storing them in the memory banks and the other control units are for controlling the associated I/O devices connected thereto using the instructions and data stored in the memory banks, the terminal controller is provided with a memory bus switch logic unit for controlling the selective connection of one of the control units to one of the memory bands so that each of the control units is connected to access the desired one of the memory banks independently of the other control units.