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Residue Checking and Signal Processors

IP.com Disclosure Number: IPCOM000040142D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Jones, GD [+details]

Abstract

The residue checking technique is utilized for concurrent error detection in a signal processor, as disclosed herein. The arithmetic section of the signal processor consists of a group of registers organized in a stack 1, an arithmetic logic unit (ALU) 2, and a parallel multiplier 3. Operands enter and exit the arithmetic section of the processor via a common data bus (CDB) 7. A 16-bit-wide data flow is assumed, although the checking technique is applicable to other data flow widths as well. The residue checking approach disclosed appends to all operands a predicted residue (PR). All operations on each operand will update the PR. The operand can be validated by computing the actual residue (R) and comparing it to the predicted PR.