Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-01
A priority encoder is described in which any non-zero bit of a string of input bits may be assigned priority, instead of only the leftmost (highest-order) non-zero bit. The relaxed requirement for assigning priority translates into reduced gate requirements. A string of 16 input bits, A0 through A15 (high to low order), is used as an example. Each of the output bits of the encoded priority address, B0 through B4, as well as the predicted output parity BP, is independently implemented from the inputs. This assures that a single error in the logic will always cause only a single error among the outputs. (Image Omitted) In Fig. 1, the input bits are rearranged while leaving the truth table intact for detecting the leading zero. The rearrangement changes the priorities among the inputs.