Interrupt Arbitration to Prevent Data Overrun
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-01
A technique is described whereby an interrupt arbitration is implemented so as to prevent an overrun condition on unbuffered interrupt devices in computers using multi-master system operation. The concept enables the CPU to maintain a higher percent of system processing time during the servicing of interrupts. Interrupt performance is improved by allowing the CPU to execute bus cycles during the time that masters are competing for the bus, when "+ARB/-GRANT" is high. The number of CPU bus cycles may be programmable. It is assumed that the Central Arbitration Unit has access to the INTR signal at the CPU. When an INTR is detected, the Central Arbitration Unit will set a latch in its diagnostic status port, which gives the CPU a special priority in the system.