Self-Timed Performance Test for Stand-Alone Random-Access Memories
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
A method for reducing the effective tester timing tolerance of memory access measurements by moving the output comparator from the tester to the chip is reported. Tester pulse timing tolerances and propagation delays are significant undesirable variables when screening high performance random- access memory (RAM) products for a guaranteed access times. To accommodate tester pulse timing tolerances and tester pulse propagation delays, chips are designed to a tighter worst-case performance specification than would otherwise be required to prevent shipment of out of specification product. By negating the tester pulse timing tolerances and timing pulse propagate delays between tester and wafer chips under test, more precise access measurements can be made.