Serial Test Clock Circuit Interface for Gate Arrays
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby a circuit interface allows the use of any number of test clocks for gate array testing, while requiring only three input/output (I/O) pins. It is an improvement over prior designs which were limited to only 16 internal test clocks. The circuit is so designed that serial test clock interfaces use three signal I/O signal pins on gate array circuitry of shift registers and demultiplexers, as shown in the figure. The three signal I/O pins are address input 10, address strobe 11 and test clock 12. Address input 10 signal and address strobe 11 signal control shift register 13 inside a gate array. Address strobe 11 is used as a clock to strobe the address input data into shift register 13.