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Non-Volatile Memory Page

IP.com Disclosure Number: IPCOM000040256D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Taber, AH [+details]

Abstract

Most strategies for replacing magnetic core memory with semiconductor memory have experienced drawbacks. For example, a battery-backed complementary metal-oxide semiconductor (CMOS) static random-access memory (SRAM) approach has a limited temperature range, limited shelf life, and can present a potential chemical hazard depending on battery technology utilized. Correspondingly, the use of electrically erasable programmable read only memories (EEPROMs) alone imposes an unrealistic limitation on the number of write cycles. A strategy which has none of the above limitations and is simple and inexpensive to implement is described in the following.