Browse Prior Art Database

ALIGNMENT MARK CONTRAST ENHANCEMENT WITH PtSi

IP.com Disclosure Number: IPCOM000040266D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Lauffer, JM Lurowist, J Pike, MB Shah, AK Travis, KJ [+details]

Abstract

This method improves alignment mark contrast when fabricating integrated circuit wafers. The use of PtSi in place of thermal SiO2 provides more clearly delineated alignment marks. During manufacture of integrated circuit devices, difficulty arises in the alignment of metallization layers to previously fabricated contact levels. Previous methods resulted in alignment marks which were etched only partially into a recessed oxide isolation (ROI) layer, causing loss of contrast due to light dispersion. A target structure in Fig. 1 includes a nitride layer 1 and an ROI layer 2 formed on a silicon substrate 3. This method uses an opaque blockout in the ROI masking layer at locations where first level auto-alignment targets and manual verniers are at the contact-masking level.