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High-Level Discretionary Wiring for Wafer Scale Integration

IP.com Disclosure Number: IPCOM000040275D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Ketchan, MB [+details]

Abstract

A technique for supplying element redundancy for wafers having a plurality of transistors is provided to permit wafer scale integration. The technique comprises: providing redundant element interconnections for the wafer elements; incorporating switches, control circuitry, and associated wiring in a testing means; providing at least one contact pad for each wafer element for contacting by a probe during testing; testing the wafer to identify a working element combination of elements in the wafer; and hard-wiring the identified working element combination using the provided redundant wafer element interconnections and the identified wafer elements.