Word Line Segmenting With Two-Dimensional Decoding
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
A segmented word line architecture is accomplished by decoding local word line segment pairs through a combination of a decoded global word line and control lines. Thus, access time of dynamic random- access memory is reduced by holding resistance and capacitance of local word lines low. The figure shows one segment of N segmented pairs of local word lines 2 and 2A. Global word line 4 is driven by global word line driver circuit 10. Control lines C1 and C2 are driven from control line driver circuit 8, and control lines C3 and C4 are driven by control line driver circuit 13. Circuits 8 and 13 may be imbedded within sense amplifier and bit switch circuit block 12. Circuit operation is described assuming active-low word lines.