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N Channel FET Structure in CMOS Technology for Use in Input Signal Level Conversion

IP.com Disclosure Number: IPCOM000040317D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Kieft, KK Moran, CW Smith, LD [+details]

Abstract

Many chip applications in CMOS technology require input signals from Emitter-Coupled Logic (ECL) circuits. A Complementary Metal-Oxide- Semiconductor (CMOS) compatible structure for an isolated N channel FET is shown in the figure for converting ECL signal levels to CMOS signal levels on a CMOS chip. A buried N+ layer 10 and an N+ wrap-around reach-through 12 make it possible to electrically isolate the P- body 14 of an N channel FET 16. With proper construction ground rules the isolation boundary formed by 10 and 12 can be connected to +5 volts 18 and the isolated tub 14 can be connected to -5 volts 20. The N channel FET 16 can then be biased, within-gate-to source limitations, to convert ECL signal voltage levels of -2.2 to -1.8 volts to CMOS levels of 0 to +5 volts without any reduction in signal strength.