Stack Length Entry Block Determination Circuitry for Computer Processors
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
A technique is described whereby a circuit, imbedded in computer architecture, provides a means of allowing faster loading and storage of instructions to a computer processor. The circuit enables a processor, similar to an IBM Series/1, to generate the stack length for stack checking during one microcycle. The concept is an improvement over previous methods which required assembly of the stack length over several microcycles. Store multiple and load multiple and branch instructions for computer processors, such as the IBM Series/1, require use of a control word to define the total number of words for the stack entry as the number of registers and user words are allocated for the control word.