Extracting Single Subfields From Error Correction Codes
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Memory systems have frequently used the idea of merging error correction bits formed on byte boundaries for the generation of error correction check bits on larger words (sometimes referred to as codes with package detection ability of dual-mode codes). To extend the coverage provided by such a scheme, bus interfaces have been proposed that have correction codes covering both the address and data fields. As the data gets closer to its destination, superfluous address bits can be discarded to accommodate smaller local busses. Protection, provided by the error correction bits, can still be maintained through the use of error correction codes (ECCs) that allow the stripping of extraneous address bits so that the data and (reduced) address are covered with minimal code regeneration.