Data Integrity Checking Via Chip Redundancies
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Printed circuit chip designs frequently have large function requirements which limit the space necessary for parity checking. Limiting parity checking to only the incoming busses accommodates these design needs by utilizing two identical chips to check each other for error. Because the chips are identical, no additional design is required. The concept is described in the following. Both chips parity check the incoming busses (AT bus in and ECI bus) independently of each other and all data flow going to output busses via registers and multiplexers, i.e.