Pipelined IBM System/370 I-Fetching and Addressing Controls for Emulation Assist Processor
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
A performance gain for an Emulation Assist Processor (EAP) is attained by using pipelined IBM System/370 instruction fetching controls. The control logic is implemented using four logically reduced truth tables (Fig. 1). The function of these four tables and associated support logic virtually eliminates the need to wait for S/370 instructions which currently reside in CACHE. These controls directly interact with a CACHE/Data Storage Unit (DSU) which provides the S/370 instructions to the EAP. The functions of the four tables are as follows: The IREQ Table determines if there is a need to request a new (Image Omitted) S/370 instruction from the DSU. The determination is based upon predicting the state of the S/370 Pre-Fetch Register (PFR) in the next machine cycle.