Browse Prior Art Database

GPI to CMOS Logic Level Converter or RECEIVER

IP.com Disclosure Number: IPCOM000040383D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Gruver, MR Strom, JD [+details]

Abstract

The converter makes use of CMOS with BIPOLAR in BiFET technology to convert GPI logic levels consisting of 0.0 to 0.5 volt for a down level and 1.5 to 2.2 volts for an up level to CMOS logic levels typically consisting of 0 to 5.0-volt swings. The figure, illustrating the converter, operates as follows: The input signal is applied to Q1 of the input differential pair. When node IN goes high, Q1 conducts and Q2 turns off. As Q1 turns on, node 5 falls to 2.8 volts below the power supply. Node 3 follows node 5 to 3.6 volts below the power supply. As node 3 falls, node 4 rises and node OUT falls, turning off T9. Node VREF1 is tied to a 1.05 volt reference. When node IN falls below this voltage, Q2 turns on. This causes node 5 to rise and node 3 follows node 5 to a diode below the power supply, turning T3 off and T4 on.