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Short Cycle Erase for Video Mode Plasma Display

IP.com Disclosure Number: IPCOM000040385D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02

Publishing Venue

IBM

Related People

Authors:
Criscimagna, TN Hoffman, HS Knecht, WR Trushell, JB [+details]

Abstract

If a CRT adapter drives a memory type of plasma panel, the vertical retrace can be used to erase all pels (picture elements) on a first scan line. This is followed by selective writing on the line and erase of the adjacent line. This process is repeated through the entire panel for a complete frame. The memory feature of the panel maintains the illumination of lit pels until the erase of the next frame, providing infinite persistence unless an update of data in a later frame leaves the pel erased at the selective write time. In order to provide high-speed operation, it is necessary to maintain fast update times of the individual pels. The erase and write cycles should be short and, if possible, combined with sustain.